i think the part that you're missing is that this is what it's like for him and people in similar regions where a huge amount of things aren't an option to begin with and many more things are far more expensive than in the US or Europe. a lot of the article is about how the best part about RISC-V is that the chips and tools are available to more of the world.
Yeah you can get <$1 STM32 dev boards and <$4 ST-Link dongles off Aliexpress. At my last job, we kept a big bag of the ST-Link dongles in the office, then whenever someone needed to debug something they could just keep the dongle attached to that board from that point on. It was a lot more convenient than having a single expensive debugger that you had to connect and disconnect.
the author just focused on his personal experiences regarding RISC-V and what he's been able to see himself as an embedded developer. there's already RISC-V SBCs that are on par with the Raspberry Pi 5 and in terms of IPC the best RISC-V cores are only lagging 5 years or less behind the best x86 and ARM cores.
no, i'm talking about the core designs, not finished CPUs you could buy. using a leading-edge node is prohibitively expensive so nearly everything RISC-V i've seen has been using around 22nm to 12nm nodes. if you had an example of any of those cores in a finished product on a similar node they should be competitive, and in the meantime once people can get their hands on them you could test them against each other at low clock speeds to see how they compare.
Then if I understood well what you said: the main bottleneck for many of those RISC-V microarchitectures is the access to the best silicon process.
(ofc, they will have to optimize them for this node process)
the current highest performance RISC-V systems you can buy off a shelf are equivalent to a raspberry pi 5 so they're not terribly behind. in terms of IPC, currently available RISC-V cores are already basically on par with Zen 3 and Apple M1 from what i understand and Jim Keller believes that RISC-V will be the one that leads the way for raw performance.
SiFive P870 and Tenstorrent Ascalon are pretty much Zen 3. Tenstorrent is supposed to be releasing silicon soon. You can license their cores now. SiFive says customers have the P870 already but I am not sure who those are.
I've seen this claimed before, and just going by SiFive's specint claims the P870 at 2.6GHz should match Zen 3.
But for SiFive's last silicon, the HiFive Premier P550, they claimed a specint2006 of 8.65/GHz. That should put the silicon only about 20% slower than an intel i5-6400. But if you look at geekbench scores it's about an order of magnitude slower.
Correct me if I'm wrong, but Tenstorrent has yet to ship any of their own cores? They do make very similar claims to SiFive.
Personally I'm very skeptical that these cores will be anywhere near Zen 3. I recon their performance claims are based on best-case CPU simulation, rather than a real measurement. I'd expect Raspberry Pi 4 levels of performance, a bit over double SiFive's current state of the art. An impressive improvement, but nowhere near Zen 3.
The P870 is probably faster than the Cortex-X1 in my phone, which would put it on a similar per level to Zen1.
When I had brief access to a very early P870 devboard running at 2GHz it scored 2% worse than an 2.86GHz Cortex-X1 in the 7-zip benchmark compression (it was a 40% worse in decompression, but that has NEON optimized Arm assembly path and non for RISC-V).
Because this was very early hardware still in bringup I expect them to get closer to the announced 2.7GHz.
But yeah, the RISC-V geekbench scores of publically available RISC-V processors are suprizingly low and idk why.
Part of it is the lack of RVV support is certain workloads, but that doesn't explain the entire gap.
When I looked at ST scalar performance my self it looked more comparible to similarly sized Arm CPUs.
I think I'll have to order a Pi5 (Cortex-A76) and investigate where it performes different to the SpacemiT K3 (SpacemiT X100).
On paper they should be very similar, both 2.4GHz, 4-wide decode, 3xALU, 1xBranch, (although the A76 has those on 4 execution units, while the X100 has 3 with one sharing ALU and Branch support), 2x load/store, 2xFP.
The biggest obvious difference (appart from ISA), may be the cache setup after L1, with the K3 having a 4Mib L2 shared between 8 cores (no L3) and the Pi5 having a 512KiB L2 and a 2MB L3 shared between 8 cores.
Well, there is some speculation regarding these chips so no sense arguing too much about it.
That said, the SpacemiT K3 is already faster than a Pi 4 and even substantially faster than a Pi 5 for multi-core and vector stuff. And that is before counting the other 8 “AI cores” it has.
These chips will be quite a bit faster than a K3, so certainly much faster than a Pi 4.
The first Ascalon silicon, Atlantis, will not be the latest process. As you say, that will impact performance. But there are plans for other chips to use newer process, and of course you can license and do what you like.
The point is that RISC-V is not limited to lower performance by the ISA.
I feel like that's largely mitigated by profiles. RVA23 is really looking like it'll be the modern base target used for high performance application processors and it makes mandatory pretty much everything you'd want for those use cases, and other comments by people familiar with designing RISC-V CPUs mention that the variable length encoding can be dealt with in a very simple manner that doesn't even add another pipeline stage so it doesn't seem like it's all that big of a deal while also bringing in benefits in code size reduction. Not everyone is adopting it, but several major players have set the stage by mandating it.
