We both know that feature sizes became marketing names over a decade ago. The "12 nm" for that fab are of course the marketing name. In any case, it's a seriously old process at this point.
I think it's still /somewhat/ close to feature size - I think the fin pitch of the "N3" tsmc process was about 5nm, which gives a "minimum feature size" of ~2.5nm to ensure the "gap" between them.
I think one of the big differences is that the "Gate Contact Area" simply isn't the smallest "feature" anymore - but the ITRS that defined those names called it "feature size", not "gate size" from the beginning intentionally.
You probably could make a transitor with a gate size of a similar order to the "feature size", it'll just perform awfully to be completely useless.
